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RIC panel discusses pathway to fusion commercialization
Fusion leaders at the Nuclear Regulatory Commission’s annual Regulatory Information Conference discussed the path forward for regulating the burgeoning fusion industry. The speakers discussed government and private industry initiatives in the United States and United Kingdom, with a focus on efforts shaping the near-term deployment of commercial fusion machines.
A recurring theme was the need to explain the difference between fission and fusion. Representatives from the Department of Energy and Type One Energy highlighted this as an important distinction for regulators, as it will allow fusion to undergo its own independent maturation process for developing standards and regulations in the same way that fission has. Lea Perlas, Fusion Program director at the Virginia Department of Health, said that confusion between fission and fusion has been a common cause for misplaced concerns among community members surrounding Commonwealth Fusion Systems’ proposed fusion plant site near Richmond, Va.
Y. Y. Azmy, B. L. Kirk
Nuclear Science and Engineering | Volume 120 | Number 1 | May 1995 | Pages 1-17
Technical Paper | doi.org/10.13182/NSE95-A24102
Articles are hosted by Taylor and Francis Online.
Mathematical performance models are developed for the parallel algorithm used to solve the neutron diffusion equation on message passing and shared memory multiprocessors represented by the Intel iPSC/860 and the Sequent Balance 8000, respectively. The performance models are validated through several test problems, and these models are used to estimate the performance of each of the two considered architectures in situations typical of practical applications, such as fine meshes and a large number of participating processors. While message passing computers are capable of producing speedup, the parallel efficiency deteriorates rapidly as the number of processors increases. Furthermore, the speedup fails to improve appreciably for massively parallel computers so that only small- to medium-sized message passing multiprocessors offer a reasonable platform for this algorithm. In contrast, the performance model for the shared memory architecture predicts very high efficiency over a wide range of number of processors reasonable for this architecture. Furthermore, the model efficiency of the Sequent remains superior to that of the hypercube if its model parameters are adjusted to make its processors as fast as those of the iPSC/860. It is concluded that shared memory computers are better suited for this parallel algorithm than message passing computers.